Last time I looked at a simple 16-bit RISC processor aimed at students. It needed a little assist on documentation as well as had a missing file, however I managed to get it to simulate utilizing a free on the internet tool called EDA Playground. This time, I’ll take you with the code details as well as exactly how to run the simulation.
You’ll want to refer to the previous publish if you didn’t checked out it already. The diagrams as well as tables provide a high-level overview that will assist you comprehend the files discussed in this post.
If you wished to really program this on a genuine FPGA, you’d have a little work to do. The memory as well as register initialization is performed in a method that works fine for simulation, however wouldn’t work on a genuine FPGA. Anyway, let’s get started!
File-by-File
If you take each data individually, none of them are extremely difficult to understand. Here’s a quick rundown (I’m utilizing the data names I’ll utilize in my on the internet simulation):
Parameter.v – This is like an include data that sets some fundamental definitions for every other file.
prog.v – This is the direction memory. A simple module, it takes an address as well as presents data for that address. The $readmemb directive reads the data from a data (test.prog).
register.v – The register file. This is almost like the direction memory however it has two checked out ports as well as you can compose to it.
data.v – The RAM memory. This is almost like the registers, however larger as well as with a single checked out port. There is some simulation code that opens a data as well as prints the memory comments, however I deleted that as it was just for debugging. The preliminary content comes from the test.data file.
alu.v – You’d believe this would be complicated, however it isn’t. It just takes two inputs as well as does something to produce the output. Something simple like adds or subtracts. The always @(*) tells Verilog not to produce clocked logic for this. It just turns into some simple gates as well as muxes.
Datapath_Unit.v – This is one of the more complex files, although if you dig into it, you’ll see it is mainly bulk. This data produces all the resources (like the registers as well as memories) as well as wires them together.
Control_Unit.v – one more longer module, this just implements the direction table, setting the control lines based on the present instruction.
ALUControl.v – This data decodes instructions for the ALU. It was missing on the original post. Oddly, there is one more similar CPU on the exact same site that has an ALUControl file, however it is clearly for a different direction set. However, starting keeping that data as well as utilizing the style table, I was able to recreate it. If [fpga4students] corrects this, the files may look extremely different.
design.sv – This data is required for the EDAPlayground simulator I’m using. It contains the top-level elements (the data path as well as the control unit). since EDAPlayground only processes this file, it is necessary for it to include the other files mentioned above. This causes some warnings since each of them has a timescale directive, however this is harmless.
testbench.sv – The testbench isn’t part of the genuine design, however just sets up the simulation as well as collects results. I had to modify it a bit to work with EDAPlayground, however the operation is the same. It just produces a CPU, feeds it a clock, as well as lets it run for a while. The test program as well as memory contents are in test.prog as well as test.data.
Simulointi
You can do one of two things. You can open up my copy of the style ready-to-go, however that may not be your finest option. I’d suggest you just go to EDAPlayground and produce a new Verilog project. then begin moving the files over from the original post. You’ll run into errors as well as missing files. See exactly how many you can fix. If you get stumped, then you can utilize my copy to assist you if you get stumped. You’ll discover more that way.
If you do choose to try it, right here are a few tips about EDAPlayground. You don’t requirement UVM/OVM selected, nor do you requirement any type of other libraries. I utilized Icarus Verilog 0.9.7, however you might most likely utilize any type of of the Verilog tools available. You do want to inspect the EPWave checkbox as well as you’ll requirement to add this to the inital part of testbench:
alkukirjain
alkaa
$dumpfile(“dump.vcd”);
$dumpvars;
Use the + indication next to the data name tabs to make new files. EDAPlayground has a limit of ten files per pane. Remember, you’ll have to include any type of .v files you produce in either testbench.sv or design.sv. You don’t requirement to include the data files since the other files utilize them indirectly.
Juosta!
Once you have all the errors worked out, you can press Run as well as you’ll get the waveform viewer, EPWave. You havE Lisää kiinnostavien signaalien signaalit niin voit katsella CPU: ta työssä. Olisi hauskaa lisätä I / O-laitteita muistiin tai joitakin virheenkorjausportteja, jotta voit katsella asioita hieman paremmin. Katson yleensä ohjelman laskurin sekä rekisterin säveltää satamaa saada käsite, mitä siellä tapahtuu.
Alkuperäisellä koodilla oli ohjelma, joka käytti paljon ohjeita. Kommentoin sitä ja korvaan sen tämän kanssa:
0000_0100_0000_0000 // 0000: TONS R0 <- MEM (R2 + 0) Koska R2 = 0 Tämä asettaa 1 R0: een 0000_0100_0100_0000 // 0002: Tons täsmälleen sama R1 (R1 sisältää aina 1) // Aseta 8 (tavu), 4 (sana): 0010_0000_0101_0000 // 0004: R2 = R0 + R1 0001_0010_1000_0000 // 0006: MEM [R1] = R2 (MEM [1] = R2 0000_0010_0000_0000 // 0008: R0 = MEM [R1] 1101_0000_0000_0011 // 000A: Hyppää sijoittaa # 4 (CPU moninkertaistaa 2 sekä Lisää 2) // Ei suuntaa 000c, mutta PC ripustaa siellä, kun se käsittelee hypätä Sinun pitäisi pystyä noudattamaan muistiin liittyvää lisäysarvoa ja katsella ohjelman vastakkaista sykliä takaisin paikalleen 4 jokaisen silmukkaan. Tässä on tyypillinen istunto: Jätin paljon sisustussignaaleja, mutta näet, että muistinosoite 1 on asetettu 2: ksi ja sitten 3: een silmukan kahdella kahdella kahdella iteraatiolla. Loppupeli Onko tämä suuri akateeminen CPU? En ole varma. Jotkut yksinkertaisemmat CPU: t ovat olemassa, mutta ne ovat usein vähän, koska ne ovat hankalia tai ne ovat erittäin epäkäytännöllisiä. Kaikki haastavampi kuin tämä on todennäköisimmin niin paljon purra aloittelijalle. Vaikka uskon, että sinulla pitäisi olla jonkin verran perustavanlaatuisen verilogin käsityksen ennen kuin käsittelet jotain tällaista, dokumentaatio oli hieman harva (ja sekava) joillakin alueilla. On selvää, että se oli suuri, koska sain sen työskentelyn, mutta jos olet juuri aloittanut, todennäköisesti arvostaisi hieman enemmän avustamista sekä selityksiä. Onko sinulla ensisijainen akateeminen Verilog CPU? Etsin edelleen, että henkilö, joka on "aivan oikein".